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Area and Power Optimization Method for High-Speed Dual VT Domino Logic with Noise Constraint

> A new design methodology for dual Vt domino logic design based on noise, area and power constraints... read more

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A Novel Technique for Reducing Subthreshold Current of VLSI Combinational Circuits

In this paper, a new technique for reducing the subthreshold leakage current of CMOS […]

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