Area and Power Optimization Method for High-Speed Dual VT Domino Logic with Noise Constraint

> A new design methodology for dual Vt domino logic design based on noise, area and power constraints is presented. We have proposed the optimum ranges for the evaluation network tree are Wmin<WN1<4Wmin and 3Wmin<WN2<5Wmin which lead to dynamic power and area improvements about 13% an  respectively. All results are based on HSPICE simulation with 0.25µm CMOS technology and operating frequency of 1GHz

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