Design of Merged Differential Cascode Voltage Switch with Pass-Gate (MDCVSPG) Logic for High-Performance Digital Systems
In this paper, a new high performance yet low power circuit technique called merged differential cascode... read more
Investigating of Bending Effect in the Design of MMIC distributed Amplifiers
The effect of bending in the design of MMIC distributed amplifiers is investigated. It […]
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Clock Delayed Domino Logic with an Efficient Variable Voltage Keeper Threshold
In this work, the domino logic with the v ariable threshold voltage keeper which […]
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مدل اصلاح شده توان آلفا براي ترانزيستورهاي MOS
در اين مقاله تغييري در مدل توان آلفا اعمال مي كنيم که ضمن افزايش […]
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The New Mixed Stochastic Power-Supply Noise-Aware Floorplanning Technique
Nowadays, with the high demand of Very Large Scale Integration (VLSI) design and also […]
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LPPM: Low Power Partitioned Multiplier
In this paper, a new architecture for low-power multipliers is proposed. The reduction of […]
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ارايه يك ساختار VLSIبهينه جهت پياده سازي تبديل موجك گسسته يك بعدي
در اين مقاله يك ساختار بهينه جهت پياده سازي تبديل موجك گسسته يك بعدي […]
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تحليل تداخل الكترومغناطيسي در منابع تغذيه سوئيچينگ
منابع تغذيه سوئيچينگ از جمله منابع نويز براي ديگر مدارها هستند. طراحي مدار به […]
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A systolic array architecture for implementing CRC on FPGA technology
Cyclic redundancy codes, CRCs, preserve the integrity of data in storage and transmissionapplications. CRC […]
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A CMOS Clock and Data Recovery Circuit for 1.25 Gb/s NRZ Data
This paper describes the PLL based clock and data recovery circuit at 1.25 Gb/s. […]
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