Pipeline Architecture for Reed-Solomon Codec

Reliability and data rate are two basic factors on QoS in mobile communication networks Th is can be achieved by addition of redundancy bits (i.e
error detection and correction codes) to refer to reliability. Reed-Solomon coding is one of the most important schemes for this purpose to achieve error correction. In this paper a pipeline approach for a RS decoder is proposed to reduce the processing time. In the pipeline architecture the number of steps to perform is in three stages, so the ideal speed up must become Because of the data dependency between the stages the achieved speed up is 1<S<1.8. The hardware description language (HDL) method is employed to hardware synthesis the Reed-Solomon encoder and decoder on FPGA devices

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