This paper suggests the design and discusses the performance of a new method for mesh architecture multiprocessing using TMS320C6000 family of DSP processors. The system is flexible, multi-dimensional and scalable Using the designed processing element (PE), the user can build up his suitable n-dimensional architecture in order to match the topology with his desired signal processing algorithm data flow The communication rate for each element is 400Mbytes/sec. This high rate is an important factor for parallel processing. An FPGA with onchip RAM is used in each processing element to enhance the communication performance of each PE with other PEs. It multiplies the communication ports number in the PE for multi-dimensional parallel processing, implements a FIFO to decouple the DSP from the com
