In this paper a new low power flip-flop called Double-edge triggered Modified Hybrid Latch FlipFlop (DMHLFF) has been proposed and compared to previous flip-flops. DMHLFF is a low power, low area, and fast flip-flop. Power consumption is reduced by avoiding unnecessary internal node transition. Power consumption in clock tree is also reduced by decreasing the frequency of clock to half of the clock frequency in single edge triggered flipflop for the same throughput. These capabilities are obtained by modifying the structure of conventional Hybrid Latch Flip-Flop without any penalty in area
