In this paper, a double-edge triggered level converter flip-flop (DE-LCFFF) is proposed. The flipflop makes use of the conditional discharging technique which effectively suppress the dynamic power consumption during transition time and the selfprecharging technique to automatically precharge its dynamic node after enough time. An explicit doubleedge pulse generator is used to further decrease the power consumption in the proposed LCFF. In addition, the use of pass gate transistors and more simplified structure in the main block of DE-LCFFF leads to a less leakage power consumption. The increase in the speed is achieved by reducing the number of the stack transistors in the discharge path and using less complicated circuit structure. When compared to the previous level converter flip-flops, the proposed LCFF shows considerable reductions in the power consumption, the delay, and the area.
Azam-Sadat Seyedi , Ali Afzali-Kusha
Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University