A Low-Power Low-Voltage Digital Compatible Analog-to-Digital Converter

 This paper describes the circuit design and architecture of a fully digital compatible Analog-toDigital Converter (ADC). The used architecture is based on current-mode Cyclic Algorithmic ADC where a digital calibration scheme based on Adaptive Algorithm is used to help to alleviate and compensate the precision requirements in the analog domain. The propose architecture can achieve high-speed and highaccuracy at low voltage power supplies with ultra low power dissipation and it does not require good device matching. The low-power digital compatible ADC has been simulated in a 0.18 μm CMOS process. Using a 1.5V power supply it achieves a dynamic range of 75 dB and the analog part of system dissipates only 0.9 mW

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