A new Implementation of DA-based IIR Filters on FPGA

FPGAs with their flexibility, parallelism high speed, and fast time-to-market are increasingly being utilized in signal processing applications. In this approach, implementation of MAC processors is one of the most challenging design tasks. One of the most suitable methods of MAC implementation on FPGAs is Distributed Arithmetic. This bit-serial word-parallel method results in very area efficient implementations reducing the resource utilization up to 80% [1 Although this method is very efficient in FIR filters, its application in IIR filters is very limited because of the inherent feedback delay in these filters, which both introduces design complexity and speed degradation. In this article, a new design of DA-based IIR filters, based on a new accumulator design, is explained, which solves the limiting problems, and achieves good area and speed performance. Results for an exemplary implementation are presente