Clock Delayed Domino Logic with an Efficient Variable Voltage Keeper Threshold

 In this work, the domino logic with the v ariable threshold voltage keeper which uses an efficient body bias is proposed. The generator which consists of a capacit or and a diode is based on the voltage doubler technique. In the proposed scheme, the keeper size may be increased to improve the noise-immunity of the domino logic with out significantly increasing the power and the delay. In addition, the proposed generator circuit is simple, consumes a smaller area, and operates with a single supply v oltage The results of simulation for a 0.18µm CMOS technology shows an improvement of 18% and 59% in power and delay, respectively, for this technique compared to the standard domino logic

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