A systolic array architecture for implementing CRC on FPGA technology

Cyclic redundancy codes, CRCs, preserve the integrity of data in storage and transmissionapplications. CRC can be used either in hardware or software implementations and it is used for error de te ction in telecommunication systems such as digital video broadcasting, mobile systems etc. In this paper the use of VLSI technology is investigated to speed up cyclic redundancy codes (CRC) circuit. The proposed structure is flexible and the systolic array is used to implement the CRC circuit. This structure can be usedپ for many number of generating polynomials (G(x

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