The class E switched mode power amplifier consists of a load network and a single transistor that is operated as a switch at the carrier frequency of th e output signal. Main three parts of the power amplif ier that specify its total efficiency are: the Q factor of output band-pass filter, the transistor on-state resistance, and the driver stage. In this paper, we design and optimize three common structures of power amplifiers using a random search algorithm. Optimized designs are simulated with HSPICE in 0.25µm CMOS technology at the carrier frequency of 5.2GHz. The maximum efficiency for each structure i s calculated, and then its bottle-neck is determined. We also achieve the total efficiency of 92.3% for the power amplifier
