In this paper a ROM-less deterministic test pattern generator (TPG) has been proposed for test per clock scheme. This TPG consists of a dimensional linear feedback shift register (2-D LFSR) and a controller. The controller configures the structure of 2-D LFSR and it has a quite simple structure and a very low area overhead. Simulated annealing algorithm is used to find the coefficient matrix of 2-D LFSR. Test application time and power consumption is significantly reduced using this technique while keeping fault coverage at 100% Compared to the previous works, the proposed method is able to generate a much larger set of deterministic test vectors with approximately the same number of flip flops. Experimental results are shown for ISCAS’85 benchmarks
